Advanced integrated circuits include multiple levels of wiring separated by inter-level dielectric layers. Vias are etched in the dielectric layers and are filled with a metallization to vertically connect the different levels of horizontal interconnections. Currently copper is the preferred metallization metal and is often used in dual-damascene interconnect structure in which the dielectric layer is etched in a two-step process to have narrow vertically extending vias etched in the lower part of the dielectric layer and wider horizontally extending trenches etched in the upper part of the dielectric layer typically interconnecting different ones of the vias. Copper is then filled into both the vias and trenches by electrochemical plating (ECP) and chemical mechanical polishing removes the excess copper plated above the trenches and over the remainder of the wafer which is not patterned with the dual-damascene structure.
However, a more complex structure is required for the fabrication and reliable operation of a integrated circuit incorporating copper metallization. The cross-sectional view of FIG. 1 illustrates a simple via 10. It like the more complicated dual-damascene structure requires additional layers beyond the copper metallization itself. A lower dielectric layer 12 is formed with a conductive feature 14 in its upper surface, which may be a copper-filled trench in the dual-damascene metallization of the lower dielectric layer 12. An upper dielectric layer 16 is deposited over the lower dielectric layer 12 and its conductive feature 14. In the recent past, the dielectric material was typically silicon dioxide, but more recently low-k dielectric materials have been implemented, such as hydrogenated oxysilicon carbide. The via 10 is then etched in the upper dielectric layer 16 to overlie the conductive feature 14. A barrier is required between the copper to be filled into the via and the dielectric material to prevent the migration of copper into the dielectric, which would increase its conductivity and create a reliability problem. A common barrier structure includes a tantalum nitride (TaN) layer 18 and a tantalum (Ta) layer 20. The TaN and Ta layers 18, 20 need to cover the sidewalls of the via 10 but preferably do not cover its bottom in order to reduce the contact resistance to the copper conductive feature 14. A copper seed layer 22 is deposited over the barrier layer 18, 20 to serve as a plating electrode and nucleation layer for the copper to be later plated into the via 10. Thereafter, the wafer is moved to the electroplating apparatus to fill the via 10 (and the trench in the upper portion of the dielectric layer 16 in the case of dual damascene) with copper.
The Ta(N) barrier layers 18, 20 and the copper seed layer 22 are all advantageously deposited by sputtering. Tantalum nitride may be sputter deposited in the same sputter chamber as the tantalum layer by reactive sputtering, in which nitrogen is admitted into the chamber to react with the tantalum atoms sputtered from the target to form tantalum nitride. Even though sputtering is a ballistic process ill suited to coating the sides of a narrow, deep hole, that is, one have a high aspect ratio, advances in sputtering technology have circumvented the problem and allowed the continued use of sputtering for further generations of integrated circuits. However, the challenges continue to mount as the via widths decrease and the aspect ratio of the vias increase. These problems arise in part by the requirement that the barrier layers be relatively thin, for example, a few nanometers as the via widths decrease to well below 40 nm. Recently, Jenn Yue Wang et al. and Ronjun Wang et al. have respectively suggested in U.S. patent application publication 2006/0251872 and U.S. patent application Ser. No. 11/511,869, filed Aug. 29, 2006, that the tantalum barrier be replaced by a tantalum ruthenium barrier. Barriers of tantalum ruthenium with high ruthenium fraction have the advantage that if the copper seed layer is discontinuous, tantalum ruthenium, even if oxidized during transfer to electroplating apparatus, is sufficiently conductive to serve at least partially as the electrode layer for electroplating.
However, a sputtered tantalum ruthenium barrier presents problems of its own. It is greatly desired to produce a barrier layer, particularly one of ruthenium tantalum, that presents an effective barrier to the after coated and plated copper. It is also greatly desired that RuTa(N) barrier layer be deposited by sputtering even though the width of the via holes has decreased and their aspect ratio increased.